COMPUTER SCIENCE - PAGE 9
1. "Count to infinity " , problem occurs in :
1) Distance Vector Routing
2) Link State routing
3) Multicast routing
4) Hierarchical Routing
Ans: 1
2. In distance vector routing algorithm , each router maintain a separate routing table with a following entries :
1) Preferred input line, estimated time
2) Preferred input line, estimated distance
3) Preferred output line, estimated time
4) Preferred output line , estimated distance
Ans: 3
3. Which of following field in IPv4 datagram is not related with fragmentation ?
1) Flag
2) Offset
3) TOS
4) Identifier
Ans: 3
4. DNS Client is also known as :
1) DNS Updater
2) DNS resolver
3) DNS handler
4) None of these
Ans: 2
5. The header length of IPv6 datagram is :
1) 10 byte
2) 20 byte
3) 40 byte
4) 60 byte
Ans: 3
6. Choose a false statement about Von Newmann's stored program computer architecture:
1) Program and data are stored in same address space in main memory
2) Allow self modifying programs
3) Programs and data are stored in secondary memory
4) Set of control signal is same for instruction and data fetch.
Ans: 3
7. Let a computer has 512 KB of main memory having one byte per word . If all the words of memory are operational then there are minimum _______ bits in ______ .
1) 18 , Data bus
2) 19 , Data bus
3) 18 , Address bus
4) 19 , Address bus
Ans: 4
8. What is the value of IEEE 754 single precision floating point number represent by binary bit string given below: 0100 0000 0110 0000 0000 0000 0000 0000
1) 3.5
2) -3.5
3) 4.8
4) -4.8
Ans: 1
9. In 4 bit two's (2's) complement notation , addition of +3 and 4 result into :
1) 1001
2) 1010
3) 1100
4) 1111
Ans: 4
10. In 5 bit signmagnitude representation result of 11111 + 00111 will be :
1) 100110
2) 00111
3) 11000
4) 10110
Ans: 3
11. Consider the following properties for combinational digital circuit ( C) and sequential digital circuit (S) : I - Output is entirely dependent on current input. II Implemented using flipflop III Output is determined by sequence of inputs . Which of the following is valid match :
1) C I, II and S III
2) C III and S I
3) C II, III and S I
4) C I and S II,III
Ans: 4
12. Which of the following statement is not true about JK flip flop ?
1) It behaves like SR flip flop when both J & K are not 1 simultaneously
2) It behaves like T Flip flop when J = K = 1
3) It behaves like D Flip flop when J = K = 1
4) When J = K = 0 , the state remain unchanged on a clock signal
Ans: 3
13. The minimum number of D flip flop needed to design a mod264 counter is :
1) 8
2) 9
3) 264
4) 265
Ans: 2
14. In _____________ addressing mode the operands are specified within the definition of instruction such as "complement accumulator " while in ____________ addressing mode operands are explicitly specified within the address field of instruction itself.
1) Implied , Immediate
2) Direct , Immediate
3) Immediate , Direct
4) Direct, Indirect
Ans: 1
15. " Effective Address = address part of instruction + content of CPU register " is applicable for which pair of addressing modes given below :
1) Register Indirect, Relative
2) Direct, Relative
3) Indirect , Indexed
4) Relative, Indexed
Ans: 4
16. Consider single accumulator (SA) , general register (GR) and stack (S) is type of CPU organization. Which of the following specifies valid number of address fields in a computational type of instruction of each organization ?
1) SA 1 , GR 2 or 3 , S 0
2) SA 2 or 3 , GR 1 , S 0
3) SA 2 or 3 , GR 1 , S 1
4) SA 0 , GR 1 , S 2 or 3
Ans: 1
17. Which of the following is not a characteristics of reduced instruction set ( RISC ) ?
1) Hardwired control
2) Relatively few addressing modes
3) Memory access limited to load and store
4) Variable length instruction formats
Ans: 4
18. Which of the following type of Data Hazard in pipelined processor is harmless hazard?
1) Read after Write (RAW)
2) Read after Read (RAR)
3) Write after Write (WAW)
4) Write after Read (WAR)
Ans: 2
19. Choose a true statement for memorymapped I/O system :
1) It uses two separate buses for memory and I/O .
2) It uses one common bus for memory and I/O but have separate control line of each .
3) It uses common bus for memory and I/O with common control lines.
4) It uses distinct instruction for I/O transfer and memory transfer operations.
Ans: 3
20. In processor P , non preemptive priority interrupts 4 , 7 , 1 , 3 , 0 , 2 , 6 arrive sequentially (low number high priority) . If when one interrupt is being handled exactly two more interrupts arrive. What is order of these interrupts handled by P :
1) 4 , 7 , 1 , 3 , 0 , 2 , 6
2) 4 , 1 , 3 , 0 , 2 , 6 , 7
3) 0 , 1 , 2 , 3 , 4 , 6 , 7
4) 4 , 1 , 0 , 2 , 3 , 6 , 7
Ans: 4
21. Which of the following is not a valid bus arbitration policy used to decide which device may use the bus at a given point of time ?
1) Daisy chain method
2) Independent request and grant method
3) Polling Method
4) DMA control method
Ans: 4
22. In a memory hierarchy access time , hit ratio pairs for cache, main and virtual memory are given by (5ns, 80%) , (100 ns , 99.5 %) and (10ms , 100 %) respectively. The closest value of average access time of hiearchy is :1
) 10032 ns
2) 10024 ns
3) 10008 ns
4) 10064 ns
Ans: 2
23. Choose a true statement :
1) SRAM bit cell uses a capacitor and a transistor
2) DRAM bit cell uses two inverters and two transistors
3) SRAMs are faster than DRAMs
4) DRAM bit cell uses two capacitors and one transistor.
Ans: 3
24. If FD denotes hardware that fetches and decode instructions then, which of the following best defines data path of processor?
1) FD + Secondary Memory + Primary Memory
2) FD + ALU + Register File
3) FD + ALU + CU
4) FD + ALU + CU + Register File
Ans: 2
25. _____________ is not included in an instruction cycle of computer processor.
1) Fetch and decode instruction
2) Handle an interrupt
3) Calculate effective address and fetch data
4) Execute instruction and store results
Ans: 2
1) Distance Vector Routing
2) Link State routing
3) Multicast routing
4) Hierarchical Routing
Ans: 1
2. In distance vector routing algorithm , each router maintain a separate routing table with a following entries :
1) Preferred input line, estimated time
2) Preferred input line, estimated distance
3) Preferred output line, estimated time
4) Preferred output line , estimated distance
Ans: 3
3. Which of following field in IPv4 datagram is not related with fragmentation ?
1) Flag
2) Offset
3) TOS
4) Identifier
Ans: 3
4. DNS Client is also known as :
1) DNS Updater
2) DNS resolver
3) DNS handler
4) None of these
Ans: 2
5. The header length of IPv6 datagram is :
1) 10 byte
2) 20 byte
3) 40 byte
4) 60 byte
Ans: 3
6. Choose a false statement about Von Newmann's stored program computer architecture:
1) Program and data are stored in same address space in main memory
2) Allow self modifying programs
3) Programs and data are stored in secondary memory
4) Set of control signal is same for instruction and data fetch.
Ans: 3
7. Let a computer has 512 KB of main memory having one byte per word . If all the words of memory are operational then there are minimum _______ bits in ______ .
1) 18 , Data bus
2) 19 , Data bus
3) 18 , Address bus
4) 19 , Address bus
Ans: 4
8. What is the value of IEEE 754 single precision floating point number represent by binary bit string given below: 0100 0000 0110 0000 0000 0000 0000 0000
1) 3.5
2) -3.5
3) 4.8
4) -4.8
Ans: 1
9. In 4 bit two's (2's) complement notation , addition of +3 and 4 result into :
1) 1001
2) 1010
3) 1100
4) 1111
Ans: 4
10. In 5 bit signmagnitude representation result of 11111 + 00111 will be :
1) 100110
2) 00111
3) 11000
4) 10110
Ans: 3
11. Consider the following properties for combinational digital circuit ( C) and sequential digital circuit (S) : I - Output is entirely dependent on current input. II Implemented using flipflop III Output is determined by sequence of inputs . Which of the following is valid match :
1) C I, II and S III
2) C III and S I
3) C II, III and S I
4) C I and S II,III
Ans: 4
12. Which of the following statement is not true about JK flip flop ?
1) It behaves like SR flip flop when both J & K are not 1 simultaneously
2) It behaves like T Flip flop when J = K = 1
3) It behaves like D Flip flop when J = K = 1
4) When J = K = 0 , the state remain unchanged on a clock signal
Ans: 3
13. The minimum number of D flip flop needed to design a mod264 counter is :
1) 8
2) 9
3) 264
4) 265
Ans: 2
14. In _____________ addressing mode the operands are specified within the definition of instruction such as "complement accumulator " while in ____________ addressing mode operands are explicitly specified within the address field of instruction itself.
1) Implied , Immediate
2) Direct , Immediate
3) Immediate , Direct
4) Direct, Indirect
Ans: 1
15. " Effective Address = address part of instruction + content of CPU register " is applicable for which pair of addressing modes given below :
1) Register Indirect, Relative
2) Direct, Relative
3) Indirect , Indexed
4) Relative, Indexed
Ans: 4
16. Consider single accumulator (SA) , general register (GR) and stack (S) is type of CPU organization. Which of the following specifies valid number of address fields in a computational type of instruction of each organization ?
1) SA 1 , GR 2 or 3 , S 0
2) SA 2 or 3 , GR 1 , S 0
3) SA 2 or 3 , GR 1 , S 1
4) SA 0 , GR 1 , S 2 or 3
Ans: 1
17. Which of the following is not a characteristics of reduced instruction set ( RISC ) ?
1) Hardwired control
2) Relatively few addressing modes
3) Memory access limited to load and store
4) Variable length instruction formats
Ans: 4
18. Which of the following type of Data Hazard in pipelined processor is harmless hazard?
1) Read after Write (RAW)
2) Read after Read (RAR)
3) Write after Write (WAW)
4) Write after Read (WAR)
Ans: 2
19. Choose a true statement for memorymapped I/O system :
1) It uses two separate buses for memory and I/O .
2) It uses one common bus for memory and I/O but have separate control line of each .
3) It uses common bus for memory and I/O with common control lines.
4) It uses distinct instruction for I/O transfer and memory transfer operations.
Ans: 3
20. In processor P , non preemptive priority interrupts 4 , 7 , 1 , 3 , 0 , 2 , 6 arrive sequentially (low number high priority) . If when one interrupt is being handled exactly two more interrupts arrive. What is order of these interrupts handled by P :
1) 4 , 7 , 1 , 3 , 0 , 2 , 6
2) 4 , 1 , 3 , 0 , 2 , 6 , 7
3) 0 , 1 , 2 , 3 , 4 , 6 , 7
4) 4 , 1 , 0 , 2 , 3 , 6 , 7
Ans: 4
21. Which of the following is not a valid bus arbitration policy used to decide which device may use the bus at a given point of time ?
1) Daisy chain method
2) Independent request and grant method
3) Polling Method
4) DMA control method
Ans: 4
22. In a memory hierarchy access time , hit ratio pairs for cache, main and virtual memory are given by (5ns, 80%) , (100 ns , 99.5 %) and (10ms , 100 %) respectively. The closest value of average access time of hiearchy is :1
) 10032 ns
2) 10024 ns
3) 10008 ns
4) 10064 ns
Ans: 2
23. Choose a true statement :
1) SRAM bit cell uses a capacitor and a transistor
2) DRAM bit cell uses two inverters and two transistors
3) SRAMs are faster than DRAMs
4) DRAM bit cell uses two capacitors and one transistor.
Ans: 3
24. If FD denotes hardware that fetches and decode instructions then, which of the following best defines data path of processor?
1) FD + Secondary Memory + Primary Memory
2) FD + ALU + Register File
3) FD + ALU + CU
4) FD + ALU + CU + Register File
Ans: 2
25. _____________ is not included in an instruction cycle of computer processor.
1) Fetch and decode instruction
2) Handle an interrupt
3) Calculate effective address and fetch data
4) Execute instruction and store results
Ans: 2
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